The present invention relates to frequency synthesizers, and more particularly to a control circuit coupled to the frequency synthesizer for enhancing the loop locking time.
A frequency synthesizer may be used in a radio receiver, for example, to generate a channel frequency signal which is used in a demodulator section to pass received information signals only within a desired channel represented by the generated channel frequency signal. Other applications of a frequency synthesizer include tone generating circuits for an electronic organ and oscillator circuits for controlling the operational frequency of a microprocessor, for example.
A frequency synthesizer generally includes a reference oscillator which generates a very stable reference frequency signal and another oscillator which is controlled by a voltage potential to generate the channel frequency signal. A feedback frequency signal is developed from the channel frequency signal via a divide-by-N circuit. A phase detector circuit operates to converge the phase of the feedback frequency signal to the phase of the reference frequency signal by adjusting the governing voltage potential of the voltage controlled oscillator. The elements of the phase detector, the voltage controlled oscillator, and the divide-by-N counter constitute, in combination, what is generally referred to as a phase locked loop.
In most phase locked loops, a storage device such as a capacitor, for example, is coupled between the phase detector and voltage controlled oscillator. The phase detector implementation governs the sourcing and sinking of current to and from the capacitor in order to adjust the voltage thereacross which governs the channel frequency of the signal generated by the voltage controlled oscillator. An example of such a phase locked loop is described in U.S. Pat. No. 4,167,711 issued to George Smoot on Sept. 11, 1979, and assigned to the same assignee as the instant application.
The magnitudes of the source and sink currents generated in the phase detector govern how rapidly the voltage controlled oscillator "sweeps" or "locks" to the desired channel frequency. However, prior art phase locked loop designs were required to generate source and sink current magnitudes which were a compromise between that required for rapid loop lock times and that required to insure loop locking when a different operating frequency was selected. These problems are best understood by examining the operation of these prior art phase locked loops, as shown in FIGS. 1A-L. In particular, FIGS. 1A-1D illustrate the prior art VCO adjustment when the VCO is operating somewhat faster than the desired operating frequency. FIGS. 1E-1H illustrate the prior art VCO adjustment when the VCO is operating slower than the desired operating frequency. And FIGS. 1I-1L illustrate the prior art VCO adjustment when the VCO is operating significantly faster than the desired operating frequency.
Referring to FIGS. 1A-1D, because the feedback clock shown in FIG. 1B was operating somewhat faster than the reference clock shown in FIG. 1A, it was necessary to provide a PUMP DOWN signal from the phase detector, as shown in FIG. 1D. However, as shown, because the phase of the reference clock lead the feedback clock, a PUMP UP signal was initially generated as shown in FIG. 1C, forcing the loop to initially speed up, after which the PUMP DOWN signal was generated providing a correction in the proper direction to the feedback clock frequency.
Referring to FIGS. 1E-1H, because the feedback clock shown in FIG. 1F was operating somewhat slower than the reference clock shown in FIG. 1E, it was necessary to provide a PUMP UP signal from the phase detector, as shown in FIG. 1G. However, as shown, because the phase of the feedback clock lead the reference clock, a PUMP DOWN signal was initially generated as shown in FIG. 1H, forcing the loop to initially slow down, after which the PUMP UP signal was generated providing a correction in the proper direction to the feedback clock frequency.
Referring to FIGS. 1I-1L, because the feedback clock shown in FIG. 1J was operating significantly faster than the reference clock shown in FIG. 1L, it was necessary to provide a PUMP DOWN signal from the phase detector. However, as shown, because the phase of the reference clock lead the feedback clock, a PUMP UP signal was initially generated as shown in FIG. 1K, forcing the loop to initially speed up, after which the PUMP DOWN signal was generated providing a correction in the proper direction to the feedback clock frequency.
In summary, incorrect loop adjustments were often generated in the prior art phase locked loops due to the operation of the phase comparison techniques. The prior art phase locked loops consequently required a careful selection of the PUMP UP and PUMP DOWN control currents to insure the loop would lock under any frequency change condition. As a result, the rate at which such loop locking could be achieved was greatly compromised, resulting in long loop locking times, often requiring many reference frequency clock periods to achieve lock. There is a need to provide a means and method for providing reduced loop locking times which are independent of the actual VCO frequency or phase encountered prior to initiating a change in the operating frequency of the phase locked loop.